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New IEEE Standard – Inactive-Withdrawn.This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance – 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.
Product Details
- Published:
- 08/03/1988
- ISBN(s):
- 9780738131535
- Number of Pages:
- 62
- File Size:
- 1 file , 9 MB
- Product Code(s):
- STDWD16766